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EDA based traffic light control system

in this design, VHDL hardware circuit description language, which is widely used at present, is selected to realize the hardware circuit description of the controller of the intersection traffic light system. It has been compiled and simulated in the EDA software platform max+plus II environment of Altera company, and downloaded to CPLD device for programming, so as to realize the control process of the traffic light system. Key words: EDA; VHDL; controller; CPLD


EDA technology is a relatively advanced technology used in electronic product design. It can replace designers to complete most of the work in electronic system design, and can directly modify errors and system functions from the program without the support of hardware circuits. It not only shortens the research and development cycle, but also greatly saves costs, and is favored by electronic engineers

there are many control methods to realize the intersection traffic light system, which can be realized by standard logic devices, programmable controller PLC, single chip microcomputer and other schemes. However, the function modification and debugging of these control methods need the support of hardware circuits. To a certain extent, the function modification and the introduction of ultracom for fiber reinforced composites by BASF are added? The difficulty of integrated technology debugging. Therefore, the electromechanical devices used in the design are stepping electromechanical and exchange servo electromechanical Da Technology. The widely used VHDL hardware circuit description language is applied to realize the design of the traffic light system controller, and the maxplus II integrated development environment is used for synthesis and simulation, which is downloaded to the CPLD programmable logic device to complete the control of the system

design requirements of traffic light system controller

like other control systems, the intersection traffic light control system is divided into two parts: controller and controlled circuit. The controller makes the whole system command the passage of vehicles and pedestrians alternately according to the set working mode, receives the feedback signal of the controlled part, determines its state transition direction and output signal, and controls the working process of the whole system

according to the actual situation of intersection traffic operation, in this continuous research and development system in terms of intelligent and automatic performance, the working conditions of the system are set as follows

the east-west road of the intersection traffic light control system has traffic lights R (red), y (yellow), G (green); East West pedestrian safety passage lights: RXR (red), RXG (green). There are traffic lights on the North-South Road: R1 (red), Y1 (yellow), G1 (green); North South pedestrian safety passage lights: rxr1 (red), rxg1 (green), all lights are on at high level. The variable mode timing circuit that sets the passing time of 15s and the conversion time of 5S, determines whether it is module 15 or module 5 by the preset input integer CNT, and the input logic CX is used to determine whether it is cleared at 4 or 14. CLK is the reference second pulse signal provided externally. X0, x1, X2, X3 are four bit binary numbers representing the counting time output by the controller. Figure 1 is a symbolic block diagram of the system controller

program design of the controller

* ASM diagram of the controller

according to the system design requirements, the ASM diagram of the controller is obtained, as shown in Figure 2. Here, all 1 The frequency conversion series resonant voltage withstand test device of Jinan experimental machine factory should be used by high-voltage experiment professionals, and the input signals are valid at high level. The ASM diagram reflects the transition process and duration of different states of the traffic light system

* VHDL program design of the controller

according to the ASM diagram of the analyzed system and the design requirements of the system, each module is programmed with VHDL language, and finally the top-level file is formed. It is compiled and simulated in max+plus II environment to check whether the compiled program runs correctly. If there is an error, it needs to be modified until it is completely passed. It should be noted that when compiling a program, you should start with the bottom program first. Only after all the bottom programs are correct can you start the compilation of the top program. This is because the top-level program is a generalization of the bottom-level program. It connects the modules of the bottom-level program, which is equivalent to gathering the functions of each module to realize the control function of the whole system. Therefore, the correctness of the bottom-level program is related to the operation result of the top-level program

in the program design of the controller, when defining the structure, there are two programming methods that can be compiled and simulated, but the results are different when analyzing the timing

(1) if defined in this way:

ARCHITECTURE con1_ arc of con1 IS

SIGNAL current_ state:state;



when debugging the program, they all passed the compilation and simulation, but in the time sequence analysis, there were results that did not work according to the set counting sequence: 14, 13, 2, 1, 0. After repeated modification and debugging, the program is modified, as defined in (2)


ARCHITECYTURE con1_ arc OF con1 IS

SIGNAL current_ state:state;




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